File llvm-targets.patch of Package cross-armv7hl-rust

diff -ur rustc-1.33.0-src/config.toml.example rustc-1.33.0-src-new/config.toml.example
--- rustc-1.33.0-src/config.toml.example	2019-02-28 09:53:34.000000000 +0100
+++ rustc-1.33.0-src-new/config.toml.example	2019-03-31 21:19:48.750629718 +0200
@@ -61,14 +61,14 @@
 # support. You'll need to write a target specification at least, and most
 # likely, teach rustc about the C ABI of the target. Get in touch with the
 # Rust team and file an issue if you need assistance in porting!
-#targets = "X86;ARM;AArch64;Mips;PowerPC;SystemZ;JSBackend;MSP430;Sparc;NVPTX;Hexagon"
+#targets = "X86;ARM;AArch64"
 
 # LLVM experimental targets to build support for. These targets are specified in
 # the same format as above, but since these targets are experimental, they are
 # not built by default and the experimental Rust compilation targets that depend
 # on them will not work unless the user opts in to building them. By default the
 # `WebAssembly` and `RISCV` targets are enabled when compiling LLVM from scratch.
-#experimental-targets = "WebAssembly;RISCV"
+experimental-targets = ""
 
 # Cap the number of parallel linker invocations when compiling LLVM.
 # This can be useful when building LLVM with debug info, which significantly